1. Field of the Invention
The invention relates to an integrated circuit device made by compound semiconductor and, more particularly, to such an integrated circuit device using a direct coupled FET logic (DCFL) circuit as a logic gate.
2. Description of the Prior Art
A compound semiconductor integrated circuit device comprising an E/R (Enhancement/Resistor) type DCFL circuit using an enhancement-mode n-channel junction FET and a load resistor which are formed on a GaAs (gallium arsenide) substrate is suitable for an ultrahigh speed LSI because an operating speed is high and an electric power consumption is low and it has a large noise margin.
FIG. 1 shows a conventional E/R type DCFL circuit and shows an example of a 2-input NOR logic circuit. As shown in FIG. 1, the E/R type DCFL circuit is a digital circuit in which a circuit comprising two enhancement-mode junction FETs Q.sub.l ' and Q.sub.2 ' and a load resistor R' which are serially connected is used as one logic gate. A positive polarity power source to supply a power source voltage V.sub.DD is connected to one end of the load resistor R'. A negative polarity power source to supply a power source voltage V.sub.SS is connected to One end (source) of each of the enhancement-mode junction FETs Q.sub.1 ' and Q.sub.2 '.
The operation of the E/R type DCFL circuit shown in FIG. 1 will now be described hereinbelow.
First, in the enhancement-mode junction FETs Q.sub.1 ' and Q.sub.2 ', when a positive voltage exceeding a threshold voltage (about 0.2 V) for source electrodes is applied to gate electrodes, a current flows between the source and drain. When a gate voltage is lower than the threshold voltage or is set to a negative potential for the source, those transistors are in the OFF state and no current flows between the source and drain.
When a voltage which is equal to or lower than the threshold voltage for the power source voltage V.sub.SS of the negative polarity power source is applied to both of input terminals A and B, the two enhancement-mode junction FETs Q.sub.1 ' and Q.sub.2 ' are turned Off and not current flows between the source and drain, so that a voltage drop due to the load resistor R' does not occur. Therefore, a voltage which is equal to the power Source voltage V.sub.DD of the positive polarity power source is generated to an output terminal OUT. On the other hand, when a voltage which is equal to or higher than the threshold voltage for the power source voltage V.sub.SS of the negative polarity power source is applied to at least one Of the input terminals A and B, the two enhancement-mode junction FETs Q.sub.1 and Q.sub.2 ' are turned on and a current flows between the source and drain, so that a voltage which is lower than the power source voltage V.sub.DD of the positive polarity power source by the voltage drop due to the load resistor R' is generated to the output terminal OUT due to the voltage drop due to the load resistor R'. A difference between those voltages is handled as logic "1" and "0".
As a DCFL circuit of a construction different from the above E/R type DCFL circuit, there is an E/D (Enhancement/Depletion) type DCFL circuit using an enhancement-mode n-channel junction FET and a depletion-mode n-channel junction FET which are formed on a GaAs substrate. Similarly to the E/R type DCFL circuit, the E/D type DCFL circuit is also suitable for an untrahigh speed LSI because an operating speed is high and an electric power consumption is low and it has a large noise margin.
FIG. 2 shows a conventional E/D type DCFL circuit and shows an example of a 2-input NOR logic circuit. As shown in FIG. 2, such an E/D type DCFL circuit is a digital circuit in which a circuit comprising two enhancement-mode junction FETs Q.sub.1 ' and Q.sub.2 ' and a depletion-mode junction FET Q.sub.3 ' (load element) which are serially connected is used as one logic gate. The E/D type DCFL circuit uses the depletion-mode junction FET Q.sub.3 ' in place of the load resistor R' in the E/D type DCFL circuit shown in FIG. 1. A positive polarity power source to supply the power source voltage V.sub.DD is connected to One end (drain) of the depletion-mode junction FET Q.sub.3 '. A negative polarity power source to supply the power source voltage V.sub.SS is connected to one end (source) of each of the enhancement-mode junction FETs Q.sub.1 ' and Q.sub.2 '.
Since the operation of the E/D type DCFL circuit shown in FIG. 2 is similar to the operation of the E/R type DCFL circuit shown in FIG. 1 except that a voltage drop occurs in the depletion-mode junction FET Q.sub.3 ', its description is omitted here.
In the compound semiconductor integrated circuit device using the above E/R type DCFL circuit or E/D type DCFL circuit, in the case where a large load capacitance due to a long wiring or the like must be driven, a circuit having excellent current drivability called a super buffer circuit (also referred to as a push pull circuit) as shown in FIG. 3 is frequently used.
As shown in FIG. 3, the super buffer circuit is a circuit in which an enhancement-mode junction FET Q.sub.4 ' and a load element L' are serially connected and an enhancement-mode junction FET Q.sub.5 ' and an enhancement-mode junction FET Q.sub.6 ' are serially connected. An FET in case of using a resistor as a load element L' corresponds to the E/R type. An FET in case of using a depletion-mode junction FET as a load element L' corresponds to the E/D type. One end of the load element L' and one end (drain) of the enhancement-mode junction FET Q.sub.6 ' are connected to a positive polarity power source to supply the power source voltage V.sub.DD. One end (source) of each of the enhancement-mode junction FET Q.sub.4 ' and the enhancement-mode junction FET Q.sub.5 ' is connected to a negative polarity power source to supply the power source voltage V.sub.SS. A common gate voltage is applied to gate electrodes of the enhancement-mode junction FETs Q.sub.4 ' and Q.sub.5 '. A connection point of the enhancement-mode junction FET Q.sub.4 ' and the load element L' is connected to a connection point of the enhancement-mode junction FETs Q.sub.5 ' and Q.sub.6 '.
The operation of the super buffer circuit shown in FIG. 3 will now be described hereinbelow.
First, in each of the enhancement-mode junction FETs Q.sub.4 ', Q.sub.5 ', and Q.sub.6 ', when a positive voltage exceeding a threshold voltage (about 0.2 V) for the source electrode is applied to the gate electrode, a current flows between the source and drain. However, when the gate voltage is lower than the threshold voltage or is set to a negative potential for the source, the FET is in the OFF state and no current flows between the source and drain.
When a voltage which is equal to or lower than the threshold voltage for the power source voltage V.sub.SS of the negative polarity power source is applied to an input terminal C, the enhancement-mode junction FET Q.sub.4 ' is turned off and no current flows between the source and drain, so that a voltage drop due to the load element L' does not occur. Therefore, a voltage which is equal to the power source voltage V.sub.DD of the positive polarity power source is applied to the gate electrode of the enhancement-mode junction FET Q.sub.6 '. Thus, the enhancement-mode junction FET Q.sub.6 ' is turned on. On the other hand, the enhancement-mode junction FET Q.sub.5 ' is in the OFF state because the same gate voltage as that of the enhancement-mode junction FET Q.sub.4 ' is applied to the gate electrode. Thus, a voltage near the power source voltage V.sub.DD Of the positive polarity power source appears at the output terminal OUT.
When a voltage which is equal to or higher than the threshold voltage for the power source voltage V.sub.SS of the negative polarity power source is applied to the input terminal C, the enhancement-mode junction FET Q.sub.4 ' is turned on and a current flows between the source and drain, so that a voltage which is lower than the power source voltage V.sub.DD of the positive polarity power source by the voltage drop due to the load resistor L' is applied to the gate electrode of the enhancements mode junction FET Q.sub.6 ' due to the voltage drop by the load element L'. Therefore, the enhancement-mode junction FET Q.sub.6 ' is turned off. On the other hand, the enhancement-mode junction FET Q.sub.5 ' is in the ON state because the same gate voltage as that of the enhancement-mode junction FET Q.sub.4 ' is applied to the gate electrode. Thus, a voltage near the power source voltage V.sub.SS of the negative polarity power source appears at the output terminal OUT. A difference between those voltages is handled as logic "1" and "0".
In the above conventional E/R type DCFL circuit shown in FIG. 1, since the output voltage from the output terminal OUT is applied to the input terminal of the circuit at the next stage, when the power source voltage V.sub.DD is increased, a voltage of 1.2 V or higher is applied to the gate electrode of the enhancement-mode junction FET at the next stage from a time point at which the power source voltage V.sub.DD exceeds 1.2 V, so that holes are injected into the GaAs substrate from the gate electrode. A switching time of the circuit increases due to the accumulation effect of the holes, so that a switching speed decreases (refer to FIG. 4). Therefore, in the conventional compound semiconductor integrated circuit device using the above E/R type DCFL circuit, the power source voltage V.sub.DD within a range from 1.0 to 1.2 V must be used. When considering the case of actually using the LSI, however, the use of the power source voltage of e.g., 1.2 V in the GaAs IC means that there is no compatibility of the power source voltage with a silicon (Si) IC. Therefore, there is a problem such that in case of using the GaAs IC together with, for instance, an Si IC, a special power supply circuit is needed for only the GaAs IC.
The above problem also similarly occurs in the conventional E/D type DCFL circuit shown in FIG. 2 mentioned above.
On the other hand, in the conventional super buffer circuit shown in FIG. 3 mentioned above, just after completion of the switching Operation, for a period of time during which the voltage at the source terminal of the enhancement-mode junction FET Q.sub.6 ', namely, the output voltage from the output terminal OUT is lower than the power source voltage V.sub.DD by the threshold voltage, that is, for a period of time when the enhancement-mode junction FET Q.sub.6 ' is ON, the load capacitance is charged at a high speed by a drain current of the enhancement-mode junction FET Q.sub.6 ' and the output voltage increases at a high speed as shown in a region 1 in FIG. 5. However, after that, when the time elapses in such a state, the load capacitance is charged little by little by a slight leak current of the enhancement-mode junction FET Q.sub.6 '. There is, consequently a problem such that the output voltage slowly rises to the power source voltage V.sub.DD of the positive polarity power source as shown in a region 2.
To solve the above problem, there is a method of increasing the power source Voltage V.sub.DD (for instance, to 2 V) and clamping the output Voltage by the rising characteristics of the diode between the gate and source of the junction FET at the next stage. According to the above method, since the output voltage is clamped by the diode between the gate and source of the junction FET at the next stage, the foregoing problem such that the output voltage slowly rises up to the power source voltage V.sub.DD does not occur. However, there is a problem such that since a voltage of 1.2 V or higher is applied to the gate electrode of the junction FET at the next stage and holes are injected into the GaAs substrate from the gate electrode, the switching speed is decreased due to the accumulation effect of the holes.